Downconversion is the process by which a radio frequency (RF) signal is stripped of its high frequency carrier wave to reveal the information carrying waveform embedded within. Needless to say, downconversion processes are implemented within virtually every radio, cell phone, two-way transceiver, pager, transponder and other device that receives information propagated via an RF signal. Received RF signals are downconverted to a baseband signal that has a form and frequency that can be manipulated using electronic components so that the information contained within can be extracted and used.
In a direct-conversion system, a received RF signal may be downconverted to a baseband analog signal using a single downconversion stage. In a multi-stage conversion system, a received RF signal may be downconverted to a baseband analog signal using multiple downconversion stages. In such multi-stage conversion systems, a received RF signal may be downconverted in a first downconversion stage to an Intermediate Frequency (IF) signal having a frequency lower than that of the original RF signal. Subsequent downconversion stages may further downconvert the IF signal produced by a preceding downconversion stage until a baseband analog signal with desired frequency characteristics is achieved. Regardless of whether a direct-conversion system or a multi-stage conversion system is used to generate the baseband analog signal, the generated baseband analog signal may be sampled by an analog-to-digital converter (ADC) to produce a baseband digital signal.
Unfortunately, due to the inconsistency of the local clocks used by the respective transmitting and receiving devices, a timing offset may exist that may cause an analog-to-digital converter (ADC) in a receiving device to sample the generated baseband analog signal using a sampling timing that is out of phase with the incoming signal. Such a condition may be described as the sampling timing not being properly locked. If not corrected, such a timing offset may, on its own, result in an increase in errors in the generated baseband digital signal and an increased frame error rate in subsequently extracted data stream due to a reduced signal-to-noise ratio in the recovered signal.
FIG. 1, presents an exemplary early-late gate timing loop 100 that may be used within a device with a single antenna receiver to control the sampling timing of the analog-to-digital converter so that the sampling timing of the analog-to-digital converter is able to remain locked to the incoming signal. As shown in FIG. 1, early-late gate timing loop 100 may include an analog-to-digital converter 102, a digital low-pass filter 104, a digital decimator 106, a digital mixer 108, a Barker correlator 110, an early-late difference generator 112 and a loop filter 124.
For example, in operation, analog-to-digital converter 102 may receive a baseband analog signal and may sample the incoming baseband analog signal at 44 MHz, e.g., at four times the chip rate, to produce a 44 MSPS (Mega-Samples Per Second) stream of, for example, digitized 6-bit sample values. Digital low-pass filter 104 may receive the 44 MSPS stream of digitized 6-bit sample values and may apply a low-pass filtering algorithm to generate a low-pass filtered stream of digitized 6-bit sample values at 44 MSPS. Digital decimator 106 may receive the low-pass filtered stream of digitized 6-bit sample at 44 MSPS and may remove every second 6-bit sample, i.e., every other 6-bit sample, to produce a stream of digitized 6-bit samples at 22 MSPS. Digital mixer 108 may receive the stream of digitized 6-bit samples at 22 MSPS and may mix the 6-bit samples with a phasor of the form e−jθ, to produce a stream of complex baseband values at 22 MSPS. Barker correlator 110 may receive the stream of complex baseband values at 22 MSPS and may correlate the incoming stream of complex baseband values with the chosen Barker code to produce a stream of correlated complex values that may be received by early-late difference generator 112. Details related to operation of the Barker correlator 110 are addressed in greater detail below.
Early-late difference generator 112 may include a switch 114 that may be selectively closed to pass a correlated complex value output from Barker correlator 110 to magnitude generator 116 at a time that is one-half chip prior to a determined bit synchronization time, or bit_sync_time. Magnitude generator 116 may generate a magnitude of the received correlated complex value. This magnitude value may be referred to as an early magnitude. Further, early-late difference generator 112 may include a switch 118 that may be selectively closed to pass a correlated complex value output from Barker correlator 110 to magnitude generator 120 at a time that is one-half chip after the determined bit_sync_time. Magnitude generator 120 may generate a magnitude of the received correlated complex value. This magnitude value may be referred to as a late magnitude. Magnitude generator 116 and magnitude generator 120 may calculate a magnitude for a received correlated complex number, such as x, using the equation,Magnitude(x)=√{square root over ((Re{x})2+(Im{x})2)}{square root over ((Re{x})2+(Im{x})2)}  EQ. 1
where Re{x} is the real, or Inphase, portion of the correlated complex value output by the Barker correlator; and
where Im{x) is the Imaginary, or Quadrature, portion of the correlated complex value output by the Barker correlator.
Early-late difference generator 112 may further include an adder 122 that may receive the early-magnitude from magnitude generator 116, receive the late-magnitude from magnitude generator 120, and subtract the generated early-magnitude from the generated late-magnitude, or vice versa, to generate a magnitude difference that may be passed to loop filter 124. Loop filter 124 may process the received magnitude difference and may generate a timing control signal that may be passed to analog-to-digital controller 102 to advance or retard the sampling timing used by analog-to-digital controller 102 to sample the analog IF signal.
For example, as shown in FIG. 1, the magnitude difference generated by difference generator 112 may be provided to a loop filter 124 that, based on the sign and magnitude of the determined difference, may generate a control signal that may be used to advance or retard sample times used by analog-to-digital converter 102. With each iteration of the loop, the loop filter may generate an adjustment to the sampling timing performed by analog-to-digital converter 102 that may change the sampling time of the analog-to-digital converter 102 so the early and late Barker correlator magnitudes are nearly equal. Assuming the slope of the Barker correlator magnitude curve, e.g., as shown in FIG. 2 at 202, is symmetrical about the peak magnitude at bit_sync_time, the difference value produced by difference generator 112 should approach zero as the analog-to-digital converter sampling approaches, i.e., locks onto, the chip rate, or frequency/phase of the baseband analog signal. The closer the lock of the analog-to-digital sampling timing, the greater the correlation between the complex digital baseband signal and the Barker code. This may result in an increased Barker correlator output magnitude at bit_sync_time.
Although not explicitly addressed above, exemplary early-late gate timing loop 100 is a circuit within a receiver device that includes additional circuits that support other functions performed by the receiver. For example, in support of exemplary early-late gate timing loop 100, the receiver device may include either a direct-conversion system or a multi-stage conversion system, as described above, that receives and downconverts an RF signal to the baseband analog signal sampled by analog-to-digital controller 102. Further, the receiver device may include a receiver controller that controls the integrated operation of respective circuits based on, for example, a state machine and/or control parameters that may be used to control and monitor processing performed by the respective circuits. For example, the receive controller may monitor the output of Barker correlator 110 and may determine and store a bit_sync_time that corresponds to a tap at which the greatest correlation between the received stream of complex baseband samples and the Barker code was achieved in prior Barker correlation cycles. Alternatively, the bit_sync_time may be determined using another processing technique using other circuitry supported by the receiver device. In either case, the controller may use its knowledge of the determined bit_sync_time to control the opening and closing of switch 114 and switch 118 within difference generator 112, i.e., ½-chip prior to the determined bit_sync_time and ½-chip after the determined bit_sync_time, respectively, as described above.
In the circuit described above with respect to FIG. 1, it is assumed that the transmitting device encodes a 1 Mbps data stream into the transmitted signal using an 11-bit Barker code. Use of an 11-bit Barker code by the transmitting device means that each symbol, e.g., a binary 0 or binary 1, has been multiplied, or spectrally spread, by the 11-bit Barker code to be represented in the transmitted signal by 11 sub-symbol intervals, referred to as chips. Accordingly, Barker correlator 110 within the receiver device may use the same 11-bit Barker code to recover or de-spread the encoded values. However, as described above with respect to FIG. 1, the stream of complex baseband values enters Barker correlator 110 at 22 MSPS. Such a sample rate represents a represents a 2× oversampling of the chip rate.
Barker correlator 110 may accommodate such oversampling by duplicating each chip in the original 11-bit Barker code. For example, an 11-bit Barker code such as “+1 +1 +1 −1 −1 −1 +1 −1 −1 +1 −1” may be represented within the Barker correlator as “+1 +1 +1 +1 +1 +1 −1 −1 −1 −1 −1 −1 +1 +1 −1 −1 −1 −1 +1 +1 −1 −1,” and used to generate a Barker code magnitude output for each of the 22 half-chip intervals.
FIG. 2 is a plot 202 of exemplary magnitude values, each magnitude generated for each correlated complex baseband sample generated by the exemplary Barker correlator within the circuit presented in FIG. 1. FIG. 2 presents a magnitude for each of 22 half-chip intervals. As represented in FIG. 2, each tap index, labeled 1 through 22, represents a half-chip increment. Therefore, the early-magnitude, indicated in FIG. 2 at tap index 11 and labeled 206, and the late-magnitude, indicated in FIG. 2 at tap index 13 and labeled 208 are each ½-chip from the bit_sync_time, indicated in FIG. 2 at tap index 12 and labeled 204. Therefore, the magnitude values at tap index 11 and at tap index 13, correspond, for example, to exemplary correlated complex baseband samples that may be passed by switch 114 and switch 118 into magnitude generators 116 and 120, respectively, for use in generating the early-late difference value produced by adder 122 and passed to loop filter 124, as described above with respect to FIG. 1.